Department of Electronics and Communication Engineering
5TH SEMESTER - 18EC56 HDL
Sunday, February 7, 2021
Verilog HDL -18EC56 MODULEWISE QUESTION BANK
Thursday, February 4, 2021
Verilog HDL -18EC56- VTU QUESTION PAPERS - Refer till Module 4
Tuesday, February 2, 2021
Verilog HDL- 18EC56 Module 5 Notes- Useful Modeling techniques / Logic Synthesis with Verilog
Monday, December 28, 2020
Verilog HDL -18EC56 -Model Question Paper
Verilog HDL- 18EC56 -Module 4 Notes-Behavioral modeling / Tasks & Functions
Sunday, December 27, 2020
Verilog HDL - 18EC56 Module 3 Notes- Gate level modeling / Dataflow modeling
Verilog HDL - 18EC56 Module 2 notes- Basic Concepts / Modules & Ports
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